1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same. Particularly, the present invention relates to a semiconductor device including a well potential supply device and a vertical MOS transistor, and to a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2009-090456, filed Apr. 2, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In forming a semiconductor device having a CMOS circuit configuration using a MOS transistor, a semiconductor substrate of one conduction type is provided with a well of a conduction type different from that of the semiconductor substrate therein, and an N- or P-type MOS transistor is arranged in the well.
At this time, the potential of the well is in a floating state, and in order to prevent an erroneous operation of the semiconductor device, a well potential fixing contact plug is connected to the well to feed a predetermined potential (Japanese Unexamined Patent Application Publication No. 2000-124450).
Japanese Unexamined Patent Application, First Publication, No. 2008-300623 discloses that in recent years, with advancement of miniaturization of semiconductor devices, instead of a known planar MOS transistor, a vertical MOS transistor including a pillar (columnar) body region (channel region) has been developed.
In the case of a CMOS circuit configuration using a vertical MOS transistor, it is also necessary to form a well and to fix the well potential.